The present invention relates to the field of thin film materials. More specifically, the invention relates to a way of depositing a thin film layer in a manner that results in the layer having desirable qualities.
The integrated circuits manufactured today typically consist of millions of devices, such as transistors, capacitors, and resistors, formed on a semiconductor substrate. Complex interconnect layers are used to connect these individual devices together in order to form the desired circuits. The quality of these interconnect layers significantly affects the performance and reliability of the fabricated integrated circuits. An interconnect layer typically includes numerous metal lines, spaced a distance apart from one another, which interconnect the devices on the semiconductor substrate. These metal lines are insulated from one another by filling the space between the adjacent lines with a dielectric material.
Manufacturers have greatly improved integrated circuit performance and yield by increasing device density and by shrinking, to the submicron level, the distances between devices fabricated on a semiconductor substrate and also the distances between the metal lines that interconnect these devices. Integrated circuit functionality is improved by connecting the devices using multiple interconnect layers stacked on top of one another. Unfortunately, as the distance between the metal interconnect lines has decreased, capacitance has increased. This is because capacitance is inversely proportional to the distance between the metal lines.
High capacitance results in problems such as increased crosstalk, increased RC delay, and increased power dissipation between metal interconnect lines. These problems may adversely affect integrated circuit performance. To prevent these interconnect problems, manufacturers of integrated circuits reduce capacitance by using low dielectric constant materials to electrically insulate devices and their interconnecting metal lines. The capacitance of the metal lines is directly proportional to the dielectric constant of the dielectric material between the metal lines. Therefore, lowering the dielectric constant of the dielectric material results in a corresponding reduction in capacitance.
To provide intralayer electrical insulation, a layer of dielectric material is deposited on each interconnect layer to fill the gaps between metal lines. When interconnect layers are stacked on top of one another, an additional layer of dielectric material may be used to provide interlayer insulation of each interconnect layer from the interconnect layers above and below it. If it has the right properties, a single layer of dielectric material can be used for both intralayer and interlayer insulation.
Alternatively, a layer of dielectric material could be deposited first. Trenches and vias can be etched into the dielectric layer and filled with a metal, such as copper, for example, to form a metal interconnect layer. Vias are vertical openings filled with a conducting material used to connect various stacked interconnect layers to one another. In forming the metal interconnect layer in this manner, the dielectric material provides intralayer insulation between the interconnect metal lines. An additional layer of dielectric material is deposited on the interconnect layer to provide interlayer insulation from the interconnect layer above it. If it has the right properties, this additional layer of dielectric material can comprise the same material as the layer of dielectric material below it.
In addition to their insulating properties, it is desirable for interlayer dielectric (ILD) materials to have a number of other properties. An ILD should have a high hardness so that it will be able to withstand chemical-mechanical planarization. An ILD should have a high modulus, or stiffness, so that it has the structural strength to support additional layers deposited on top of it. High hardness and modulus values also allow for via formation through the ILD between adjacent interconnect layers. It is also desirable that an ILD material be thermally stable so that it does not degrade or release harmful substances during subsequent high temperature processing steps during manufacturing.
Silicon dioxide (SiO2) has been the most commonly used ILD in semiconductor manufacturing. SiO2 is thermally stable and has a high hardness, a high modulus, and a dielectric constant (k) of approximately 4. Dielectric constants are determined for various materials based on a scale where 1 represents the dielectric constant of a vacuum. Although SiO2 has a number of desirable properties that make it readily adaptable to the manufacturing environment, its relatively high dielectric constant has limited the ability of integrated circuit manufacturers to further increase device density and decrease the distances between the interconnect lines. There exists a need for a low-k ILD material with a dielectric constant less than that of SiO2, a high hardness, a high modulus, and a high thermal stability.
Briefly, an amorphous fluorocarbon (CxFy) material layer is described. This material layer has a number of desirable qualities, including a high hardness, a high modulus, and high thermal stability. These qualities make the material layer especially useful as an interlayer low-k dielectric material in integrated circuit manufacturing.
In a further aspect of the present invention, a method of depositing a thermally stable, mechanically hard, and elastic dielectric material layer is described. The dielectric material layer is deposited using a plasma reactor. Helium is used as the plasma gas. The use of helium results in a dielectric material layer with a high hardness, a high modulus, and a high thermal stability.